摘要
Design and performance of UTSi CMOS down converter RFIC for CDMA applications is presented. The down converter consists of two-stage LNA, RF switch, and mixer integrated with passive matching components. Performance of building blocks have been evaluated. Results show that the stringent requirements for linearity at low power consumption required for CDMA can be achieved using UTSi CMOS technology. By integrating the down converter with PLL fabricated in the same process, it will be possible to realize a single chip transceiver IC. Results show that Silicon CMOS UTSi have the on-chip RF performance required for high level of integration of future wireless communications systems.
| 原文 | 英語 |
|---|---|
| 主出版物標題 | IEEE Radio Frequency Integrated Circuits Symposium, RFIC, Digest of Technical Papers |
| 發行者 | IEEE |
| 頁面 | 181-184 |
| 頁數 | 4 |
| ISBN（列印） | 0780356047 |
| 出版狀態 | 已發佈 - 1月 1 1999 |
| 對外發佈 | 是 |
| 事件 | Proceedings of the 1999 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium - Anaheim, CA, USA 持續時間: 6月 13 1999 → 6月 15 1999 |
會議
| 會議 | Proceedings of the 1999 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium |
|---|---|
| 城市 | Anaheim, CA, USA |
| 期間 | 6/13/99 → 6/15/99 |
ASJC Scopus subject areas
- 工程 (全部)