Mismatch independent DNL pipelined analog to digital converter

John Wu; Bosco Leung; Sehat Sutarja

Mismatch independent DNL pipelined analog to digital converter

John Wu
, Bosco Leung
, Sehat Sutarja

研究成果: 雜誌貢獻 › Conference article › 同行評審

摘要

A pipelined ADC based upon a new error correction algorithm is presented. With a 10% mismatch in capacitor sizes the proposed ADC achieves a simulated DNL (differential non-linearity) of 9 bits can be realized. Spice level simulations based upon extracted layout of the chip designed in a 1.2 mm CMOS process show that 3.3 MSampAles/s can be resolved at 20 mW per bit.

原文	英語
頁（從 - 到）	461-464
頁數	4
期刊	Proceedings - IEEE International Symposium on Circuits and Systems
卷	5
出版狀態	已發佈 - 12月 1 1994
對外發佈	是
事件	Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England 持續時間: 5月 30 1994 → 6月 2 1994

ASJC Scopus subject areas

電氣與電子工程
電子、光磁材料

其它文件與鏈接

Link to publication in Scopus

引用此

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title = "Mismatch independent DNL pipelined analog to digital converter",

abstract = "A pipelined ADC based upon a new error correction algorithm is presented. With a 10\% mismatch in capacitor sizes the proposed ADC achieves a simulated DNL (differential non-linearity) of 9 bits can be realized. Spice level simulations based upon extracted layout of the chip designed in a 1.2 mm CMOS process show that 3.3 MSampAles/s can be resolved at 20 mW per bit.",

author = "John Wu and Bosco Leung and Sehat Sutarja",

year = "1994",

month = dec,

day = "1",

language = "English",

volume = "5",

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journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

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publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) ; Conference date: 30-05-1994 Through 02-06-1994",

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T1 - Mismatch independent DNL pipelined analog to digital converter

AU - Wu, John

AU - Leung, Bosco

AU - Sutarja, Sehat

PY - 1994/12/1

Y1 - 1994/12/1

N2 - A pipelined ADC based upon a new error correction algorithm is presented. With a 10% mismatch in capacitor sizes the proposed ADC achieves a simulated DNL (differential non-linearity) of 9 bits can be realized. Spice level simulations based upon extracted layout of the chip designed in a 1.2 mm CMOS process show that 3.3 MSampAles/s can be resolved at 20 mW per bit.

AB - A pipelined ADC based upon a new error correction algorithm is presented. With a 10% mismatch in capacitor sizes the proposed ADC achieves a simulated DNL (differential non-linearity) of 9 bits can be realized. Spice level simulations based upon extracted layout of the chip designed in a 1.2 mm CMOS process show that 3.3 MSampAles/s can be resolved at 20 mW per bit.

UR - https://www.scopus.com/pages/publications/0028589747

UR - https://www.scopus.com/pages/publications/0028589747#tab=citedBy

M3 - Conference article

AN - SCOPUS:0028589747

SN - 0271-4310

VL - 5

SP - 461

EP - 464

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6)

Y2 - 30 May 1994 through 2 June 1994

ER -

Mismatch independent DNL pipelined analog to digital converter

摘要

ASJC Scopus subject areas

其它文件與鏈接

指紋

引用此