TY - JOUR
T1 - Mismatch independent DNL pipelined analog to digital converter
AU - Wu, John
AU - Leung, Bosco
AU - Sutarja, Sehat
PY - 1994/12/1
Y1 - 1994/12/1
N2 - A pipelined ADC based upon a new error correction algorithm is presented. With a 10% mismatch in capacitor sizes the proposed ADC achieves a simulated DNL (differential non-linearity) of 9 bits can be realized. Spice level simulations based upon extracted layout of the chip designed in a 1.2 mm CMOS process show that 3.3 MSampAles/s can be resolved at 20 mW per bit.
AB - A pipelined ADC based upon a new error correction algorithm is presented. With a 10% mismatch in capacitor sizes the proposed ADC achieves a simulated DNL (differential non-linearity) of 9 bits can be realized. Spice level simulations based upon extracted layout of the chip designed in a 1.2 mm CMOS process show that 3.3 MSampAles/s can be resolved at 20 mW per bit.
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M3 - Conference article
AN - SCOPUS:0028589747
SN - 0271-4310
VL - 5
SP - 461
EP - 464
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
T2 - Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6)
Y2 - 30 May 1994 through 2 June 1994
ER -