Mismatch independent DNL pipelined analog to digital converter

John Wu; Bosco Leung; Sehat Sutarja

Mismatch independent DNL pipelined analog to digital converter

John Wu, Bosco Leung, Sehat Sutarja

Research output: Contribution to journal › Conference article › peer-review

Abstract

A pipelined ADC based upon a new error correction algorithm is presented. With a 10% mismatch in capacitor sizes the proposed ADC achieves a simulated DNL (differential non-linearity) of 9 bits can be realized. Spice level simulations based upon extracted layout of the chip designed in a 1.2 mm CMOS process show that 3.3 MSampAles/s can be resolved at 20 mW per bit.

Original language	English
Pages (from-to)	461-464
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	5
Publication status	Published - Dec 1 1994
Externally published	Yes
Event	Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England Duration: May 30 1994 → Jun 2 1994

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Cite this

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title = "Mismatch independent DNL pipelined analog to digital converter",

abstract = "A pipelined ADC based upon a new error correction algorithm is presented. With a 10% mismatch in capacitor sizes the proposed ADC achieves a simulated DNL (differential non-linearity) of 9 bits can be realized. Spice level simulations based upon extracted layout of the chip designed in a 1.2 mm CMOS process show that 3.3 MSampAles/s can be resolved at 20 mW per bit.",

author = "John Wu and Bosco Leung and Sehat Sutarja",

year = "1994",

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language = "English",

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journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

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AU - Wu, John

AU - Leung, Bosco

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N2 - A pipelined ADC based upon a new error correction algorithm is presented. With a 10% mismatch in capacitor sizes the proposed ADC achieves a simulated DNL (differential non-linearity) of 9 bits can be realized. Spice level simulations based upon extracted layout of the chip designed in a 1.2 mm CMOS process show that 3.3 MSampAles/s can be resolved at 20 mW per bit.

AB - A pipelined ADC based upon a new error correction algorithm is presented. With a 10% mismatch in capacitor sizes the proposed ADC achieves a simulated DNL (differential non-linearity) of 9 bits can be realized. Spice level simulations based upon extracted layout of the chip designed in a 1.2 mm CMOS process show that 3.3 MSampAles/s can be resolved at 20 mW per bit.

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M3 - Conference article

AN - SCOPUS:0028589747

SN - 0271-4310

VL - 5

SP - 461

EP - 464

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6)

Y2 - 30 May 1994 through 2 June 1994

ER -

Mismatch independent DNL pipelined analog to digital converter

Abstract

ASJC Scopus subject areas

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